1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device such as a flash memory having a storage region constructed by a plurality of electrically rewritable nonvolatile memory cells and a booster circuit for boosting a power source voltage to generate a voltage necessary to rewrite the storage region. The present invention also relates to an IC module and an IC card each having the nonvolatile memory device and, more particularly, to a power consumption adjusting function (power management function) of the IC module and the IC card.
2. Description of the Related Art
An example of a nonvolatile semiconductor memory device having a storage region constructed by a plurality of electrically rewritable nonvolatile memory cells may include a flash memory. FIG. 4 shows the structure of a typical cell in a flash memory. The cell has a configuration capable of storing data of one bit (two values) or three or more values per one cell, and is constructed by a control gate 51, a floating gate 52, a source 53 and a drain 54. The cell is called a floating gate-type field effect transistor. The source 53 is provided commonly for memory cells of a predetermined amount (e.g., a block). A memory array (memory array block) has “n×m” memory cells arranged in an array as shown in FIG. 5. The memory array has “m” word lines connected to “n” control gates of each memory cell column and “n” bit lines connected to “m” drains in each memory cell row.
Next, the operation of the flash memory will be briefly described. Data is programmed to a memory cell by applying a high voltage (e.g., 12 V) from a selected word line to the control gate; applying a high voltage (e.g., 7 V) from a selected bit lint to the drain; applying a low voltage (e.g., 0 V) to the source; and injecting hot electrons generated in the vicinity of the drain junction to the floating gate.
On the other hand, data in the memory cell is erased by applying a low voltage (e.g., 0 V) to the control gate; applying a low voltage (e.g., 0 V) to the drain; applying a high voltage (e.g., 12 V) to the source; generating a high electric field between the floating gate and the source; and extracting electrons in the floating gate to the source side by using the tunnel effect.
In the flash memory, the threshold voltage of the floating gate-type field effect transistor as a component of the memory cell changes according to the amount of electrons in the floating gate in the memory cell. In a program state, the threshold voltage is high. In an erase state, the threshold voltage is low. Data is stored by using the phenomenon.
Further, data is read from a memory cell by applying a high voltage (e.g., 5 V) to the control gate; applying a low voltage (e.g., 1 V) to the drain; applying a low voltage (e.g., 0 V) to the source; amplifying the difference between memory cell currents according to different threshold voltages flowing in the bit lines by a sense amplifier; and determining “1” or “0” of data (in the case of binary data).
The reason why the voltage of the drain is set to be lower than that in the control gate in programming is to prevent as much as possible a parasitic weak programming voltage (soft program) from being applied to a memory cell to which data is not programmed. The soft program occurs since a plurality of memory cells are commonly connected to the same word line or the same bit line.
In order to program and erase data to/from a flash memory (hereinafter, the operations will be generically simply referred to as “rewrite”) while maintaining high reliability as described above, very complicated control is required. Consequently, many semiconductor devices in each of which a recent flash memory is mounted have therein a control circuit called a state machine and realize automatic rewriting when seen from the user in order to improve usability of the user. For example, in flash memories disclosed in JP 8(1996)-64000 A, JP 11(1999)-86580 A, JP 2001-357684A and the like, a control is performed by using a control circuit called a state machine.
FIG. 7 shows a concrete configuration example of the flash memory. A memory array 24 is an array of memory cells having the configuration shown in FIG. 5. Word lines are connected to a row decoder 22, and bit lines are connected to a column decoder 23.
A booster circuit 30 operates in programming and erasing of data and generates a high voltage (e.g., 12 V) necessary for the operation. A program/erase voltage generation circuit 21 is a circuit for generating a high voltage necessary for a rewriting operation from the high voltage (e.g., 12 V) boosted by the booster circuit 30. For example, a high voltage (e.g., 7 V) to be applied to the drain of a memory cell in programming is generated by decreasing the voltage via a regulator circuit (not shown) in the program/erase voltage generation circuit 21. A voltage to be applied to the control gate of the memory cell in programming is supplied via the row decoder 22 and a word line from the program/erase voltage generation circuit 21. A voltage to be applied to the drain is supplied via the column decoder 23 and a bit line. A voltage to be applied to the source of the memory cell in erasing is supplied via a source voltage switching circuit (not shown) from the program/erase voltage generation circuit 21.
With respect to 5 V to be applied to the control gate of the memory cell in reading, when Vcc is lower than 5 V (e.g., 3.3 V), 5 V is generated by the booster circuit 30 and supplied via the row decoder (not shown).
A control circuit 41 controls, in a rewriting operation, the booster circuit 30, the program/erase voltage generation circuit 21, the row decoder 22, the column decoder 23, a sense amplifier 25, an input/output buffer 27, an address register 26, a reference voltage generation circuit 31, a read data register 28 and a program data register 29 via a control bus on the basis of a predetermined algorithm.
A general flash memory has two kinds of power sources: a power source necessary for all of operations (hereinafter, described as Vcc); and a power source necessary only in rewriting hereinafter, described as Vpp). In rewriting of a memory cell, the power source voltage Vpp is boosted by the booster circuit 30. In reading, for example, when Vcc is lower than 5 V, the power source voltage Vcc is boosted by the booster circuit 30.
A recent flash memory using only the power source voltage Vcc is also commercially available. In this case, the power source voltage Vcc is supplied to the booster circuit 30 and a desired voltage is generated from the power source voltage Vcc.
The flowchart of FIG. 11 shows an algorithm (procedure) of a programming operation of a flash memory. A case where the power source voltages Vcc and Vpp are provided will be described. When the programming operation starts, first, program data as an expectation value is input to the program data register 29 (#10). The booster circuit 30 and the program/erase voltage generation circuit 21 are sequentially enabled (operable) (#20, #30). The flash memory waits until the program/erase voltage generation circuit 21 becomes ready to output a desired voltage, and a voltage detection circuit 37 checks a voltage level which may be the power source voltage (Vpp), an output voltage of the booster circuit or an output voltage of the program/erase voltage generation circuit 21 (#40). In the case where the voltage level is lower than a desired reference voltage (e.g., Vpp is 2.7 V or less and an output voltage of the booster circuit is 8.5 V or less), a program voltage is not applied to a memory cell but a “program operation failure” state is set.
In the case where the voltage level has achieved a desired reference voltage, a program voltage is applied to the memory cell (#50). The program voltage is applied to, in the case of a binary memory cell, a memory cell corresponding to a bit of a data value “0” in program data. Generally, in the flash memory, the data value of the memory cell in an erase state is “1”, so that it is unnecessary to program the program data “1” to a corresponding memory cell. For example, when program data length is 16 bits and program data is FFEEH (H indicates that FFEE is hexadecimal data), to be specific, in the case of “1111111111101110”, data is programmed in the bit 0 (the least significant bit) and the bit 4 (the fifth bit from the bottom). In the case where the number of memory cells to which a program voltage can be applied simultaneously (hereinafter, simply referred to as the number of program bits) is two bits, program data is divided into eight pieces and a program voltage applying operation is repeated eight times (#50, #60). However, in the case where the divided program data in the 2-bit unit is “11”, the program voltage is not applied to memory cells corresponding to the two bits. After completion of the program voltage application, a verifying operation (reading for verifying the program data) is performed (#70).
The data value of a memory cell is converted to data of “1” and “0” by the sense amplifier 25 and the data is stored into the read data register 28. The control circuit 41 compares the program data register 29 and the read data register 28 (#80). When a result of comparison is a mismatch, the program voltage is applied again to the memory cell of the mismatch (#90, #40, #50 . . . ). In the case where a match is not obtained in the verifying operation within the preset maximum number (e.g., 128) of application times, the program/erase voltage generation circuit 21 and the booster circuit 30 are disabled (inoperable) to finish the operation, and a “program operation failure” state is set (#90 to #110). In the case where a match is obtained in the verifying operation, the program/erase voltage generation circuit 21 and the booster circuit 30 are disabled (inoperable) to finish the operation, and a “program operation success” state is set (#120, #130).
FIG. 8 shows a configuration example of the booster circuit 30. The booster circuit 30 in FIG. 7 is the booster circuit 30 in FIG. 8. The booster circuit 30 is constructed by an oscillation circuit 36, a drive signal generation circuit 33, a pump cell circuit 34, a comparator 32 and a diode chain 35. The voltage is boosted by driving the pump cell circuit 34. A drive signal PCLK is generated by the drive signal generation circuit 33 on the basis of an output signal OSC of the oscillation circuit 36. To one of input terminals of the comparator 32, a voltage V12 obtained by decreasing an output V11 of the booster circuit 30 via the diode chain 35 is input. To the other input terminal of the comparator 32, a voltage V13 generated by the reference voltage generation circuit 31 is input. The reference voltage generation circuit 31 outputs a constant voltage without being hardly influenced by the power source voltage, temperature and manufacturing variations. The voltage value of the voltage V12 is connected to the diode chain 35 so as to be equal to the voltage V13 when the booster circuit 30 outputs a desired voltage (e.g., 12 V). For example, when the output voltage of the reference voltage generation circuit 31 is 2 V, it is sufficient to set six diodes in the diode change 35 and connect the voltage between the first and second diodes from the ground (ground potential) side. The voltage V12 is a voltage of ⅙ of the voltage V11, that is, 2 V. The comparator 32 compares the voltage values of the voltages V12 and V13 and outputs a bias signal BIAS for adjusting the oscillation frequency of the oscillation circuit 36. The oscillation frequency decreases as the output voltage V11 of the booster circuit 30 increases.
The configuration of an IC module mounted on a non-contact IC card will now be described. The non-contact IC card is widely used for a lift ticket in a skiing area and a tag for cloth and, recently, also used for a commutation ticket of a public institution and the like. FIG. 6 shows the configuration of an IC module mounted on a typical non-contact IC card. Internal blocks of an LSI for an IC card are a CPU core 40, a non-contact interface 10 and an antenna 15. The non-contact interface 10 is constructed by a rectification circuit 11, a modulation circuit 12, a demodulation circuit 13, a clock separating circuit 14, and regulators 16 and 17. The CPU core 40 has a configuration almost the same as that of a normal microcomputer and includes the control circuit 41, a ROM 42, a RAM 43 and a flash macro 20. A program is stored in the ROM 42, and the RAM 43 is used as a working memory during arithmetic operation. The flash macro 20 is used for storing a program or holding data and has a configuration as shown in FIG. 7.
An access from the outside is made by a signal obtained by converting an electromagnetic wave input/output via the antenna 15. An access to the memory is made by a program. A general LSI for an IC card has a one-chip configuration, so that the memory cannot be directly accessed from the outside. Therefore, an illegal access to the memory can be controlled by software and the high confidentiality of information in the memory can be realized.
A basic operation of the IC module mounted on the non-contact IC card will now be described. First, a control signal of the non-contact IC card is converted by an external reader/writer (not shown) into an electromagnetic wave and the resultant signal is supplied. When the control signal converted to the electromagnetic wave is received by the non-contact IC card, electromagnetic induction occurs by the antenna 15 buried in the non-contact IC card. A signal generated by the electromagnetic induction is converted to supply power, a clock signal and a control signal for operating the CPU core 40. The signal generated by the electromagnetic induction is converted to a positive voltage via the rectification circuit 11 and smoothed via the regulator 16 (which generates Vpp) and the regulator 17 (which generates Vcc). The resultant voltage is supplied as a power source to the CPU core 40. The power source voltage (Vcc and Vpp) of a general IC module is 5 V or 3.3 V The signal generated by the electromagnetic induction is converted to an internal clock by the clock separating circuit 14. The frequency of the internal clock is about 1 MHz to 5 MHz. Further, the signal generated by the electromagnetic induction is supplied to the control circuit 41 in the CPU core 40 via the demodulation circuit 13. By the signal supplied to the control circuit 41, the ROM 42, RAM 43 and flash macro 20 are controlled and a process such as an arithmetic operation is performed. A result of computation in the CPU macro core is converted to an AC signal having a predetermined bandwidth by the modulation circuit 12, and an electromagnetic wave is output from the antenna 15. The external reader/writer receives the electromagnetic wave, converts it to a signal via the demodulation circuit in the reader/writer, and completes transmission/reception of information to/from the IC card.
In the non-contact operation, however, under a condition that makes the magnetic field intensity low such as a long distance between the IC module and the reader/writer, the current supply capability deteriorates. Consequently, when an operation requiring a large current consumption is performed (e.g., a rewriting operation of the flash memory), even if the power source voltage reaches a desired voltage on start of the operation, a drop in the power source is caused by the current consumption in the programming operation of the regulators 16 and 17. There is a case where the high voltage generated by the booster circuit 30 cannot achieve a desired voltage level and the programming operation fails. As described above, the conventional nonvolatile semiconductor memory device having the booster circuit has a problem in that, when the current supply capability of the power source voltage drops in rewriting, the rewriting operation fails.